An 8K@120fps Hardware Implementation for Decoder-Side Motion Vector Refinement in VVC.
Jiahao LiuLeilei HuangShushi ChenWei LiYibo FanPublished in: ISCAS (2024)
Keyphrases
- hardware implementation
- motion vectors
- error concealment
- fpga implementation
- motion estimation
- video coding standard
- video coding
- motion compensation
- video sequences
- bit rate
- macroblock
- motion compensated frame interpolation
- wyner ziv
- signal processing
- video codec
- high definition
- block matching
- pixel domain
- efficient implementation
- reference frame
- motion field
- frame rate
- compressed domain
- motion estimation algorithm
- computational complexity
- frame interpolation
- low complexity
- bitstream
- real time
- image processing algorithms
- distributed video coding
- video transmission
- coding efficiency
- field programmable gate array
- high speed
- video data
- prediction error
- video quality
- rate distortion
- motion compensated
- low cost
- parallel architecture
- temporal correlation
- video compression
- error propagation
- image sequences
- block size
- video coder
- error resilient
- optical flow
- prediction scheme
- coding method
- error resilience
- inter frame
- visual quality
- moving objects
- pattern recognition
- high quality