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Impact evaluation of logic blocks configuration on FPGA's soft error rate estimation.

Fábio B. ArmelinLírida A. B. NavinerRoberto d'AmoreIrany A. Azevedo
Published in: ICECS (2016)
Keyphrases
  • error rate
  • test set
  • estimation error
  • hardware implementation
  • cost sensitive classification
  • multi class
  • modal logic
  • rejection rate
  • data sets
  • feature vectors