An FPGA Implementation of Two-Input LUT Based Information Bottleneck LDPC Decoders.
Bo-Yu TsengBrian M. KurkoskiPhilipp MohrGerhard BauchPublished in: MOCAST (2022)
Keyphrases
- information bottleneck
- fpga implementation
- information theoretic
- hardware implementation
- information bottleneck method
- multi feature
- real time
- decoding algorithm
- machine learning
- computer vision
- high level
- multiscale
- mutual information
- signal processing
- field programmable gate array
- statistical relational learning