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FATE: Fast and Accurate Timing Error Prediction Framework for Low Power DNN Accelerator Design.
Jeff Zhang
Siddharth Garg
Published in:
CoRR (2018)
Keyphrases
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low power
power consumption
single chip
low cost
high speed
logic circuits
low power consumption
vlsi architecture
power dissipation
design process
digital signal processing
prediction error
cmos technology
design considerations
power reduction
mixed signal
vlsi circuits
ultra low power