Memory-processor co-scheduling for real-time tasks on network-on-chip manycore architectures.
Chawki BenchehidaMohammed Kamel BenhaouaHoussam-Eddine ZahafGiuseppe LipariPublished in: Int. J. High Perform. Syst. Archit. (2022)
Keyphrases
- real time
- parallel architectures
- network on chip
- memory management
- multi processor
- high speed
- interconnection networks
- packet switched
- single instruction multiple data
- parallel processing
- scheduling problem
- multi core processors
- graphics processing units
- shared memory
- parallel processors
- processing elements
- data transfer
- routing algorithm
- scheduling algorithm
- parallel algorithm
- data acquisition
- signal processing
- low cost
- general purpose
- sensor networks