A memory-based architecture for FPGA implementations of low-density parity-check convolutional decoders.

Stephen Bates Gary Block

Published in: ISCAS (1) (2005)

Keyphrases

hardware architectures
decoding algorithm
low density parity check
network architecture
ldpc codes
hardware implementation
real time
vlsi architecture
low cost
high speed
vlsi implementation
message passing
error correction
error resilience