Login / Signup
A 10 Gb/s wire-speed firewall system using reconfigurable processors.
Masaru Katayama
Hidenori Kai
Junichi Yoshida
Hiroki Yamada
Kohei Shiomoto
Naoaki Yamanaka
Published in:
ICC (2005)
Keyphrases
</>
high speed
real time
parallel algorithm
general purpose
parallel processing
low cost
intrusion detection
network traffic
signal processing
computer networks
induction motor
heterogeneous computing