Login / Signup
Exploring power reduction options for a single-chip multiprocessor through system-level modeling.
Patrick Anthony La Fratta
James M. Baker Jr.
Published in:
J. Embed. Comput. (2006)
Keyphrases
</>
single chip
low power
power reduction
highly parallel
power consumption
low cost
high speed
real time
pattern recognition
image analysis
digital images
signal processing
fine grained
power saving
embedded processors