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Enhanced write performance of a 64-mb phase-change random access memory.

Hyung-Rok OhBeak-Hyung ChoWoo Yeong ChoSangbeom KangByung-Gil ChoiHye-Jin KimKi-Sung KimDu-Eung KimChoong-Keun KwakHyun-Geun ByunGitae JeongHong-Sik JeongKinam Kim
Published in: IEEE J. Solid State Circuits (2006)
Keyphrases
  • random access memory
  • design considerations
  • low voltage
  • data structure
  • inter frame
  • memory access