Hardware Architecture of the Fast Mode Decision Algorithm for H.265/HEVC.
Wenjun ZhaoTakao OnoyeTian SongPublished in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2015)
Keyphrases
- hardware architecture
- intra prediction
- video compression
- hardware implementation
- coding efficiency
- spatial correlation
- mode decision
- hardware architectures
- video coding standard
- pixel wise
- macroblock
- field programmable gate array
- bit rate
- motion compensation
- video coding
- video transmission
- processing elements
- motion compensated
- coding method
- associative memory
- rate distortion
- block matching motion estimation
- video quality
- efficient implementation
- general purpose