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Automatic testcase synthesis and performance model validation for high performance PowerPC processors.
Robert H. Bell Jr.
Rajiv R. Bhatia
Lizy K. John
Jeff Stuecheli
John Griswell
Paul Tu
Louis Capps
Anton Blanchard
Ravel Thai
Published in:
ISPASS (2006)
Keyphrases
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model validation
embedded processors
semi automatic
parallel algorithm
operating system
distributed memory
program synthesis
real time
data sets
neural network
general purpose
fully automatic
parallel processing
parallel execution
highly parallel
signal processor