A Reconfigurable Bit-Serial VLSI Systolic Array Neuro-Chip.
Paul J. MurtaghAh Chung TsoiPublished in: J. Parallel Distributed Comput. (1997)
Keyphrases
- systolic array
- reconfigurable architecture
- vlsi design
- vlsi implementation
- data flow
- high speed
- chip design
- single chip
- parallel architecture
- random access memory
- signal processing
- neural network
- artificial neural networks
- power dissipation
- neuro fuzzy
- low power
- databases
- physical design
- power consumption
- low voltage
- processor array