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Design and Analysis of Ultra Low Power True Single Phase Clock CMOS 2/3 Prescaler.

Manthena Vamshi KrishnaManh Anh DoKiat Seng YeoChirn Chye BoonWei Meng Lim
Published in: IEEE Trans. Circuits Syst. I Regul. Pap. (2010)
Keyphrases
  • ultra low power
  • high speed
  • low power
  • single phase
  • power consumption
  • real time
  • artificial neural networks
  • circuit design
  • simulation model
  • single chip
  • power dissipation