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Celerity Hardware Implementation of the AES with Data Parallel and Pipelining Architecture inside the Round Function.

Shouwen YangHui LiXiaotao ZhangGang Zhao
Published in: TrustCom/ISPA/IUCC (2013)
Keyphrases
  • hardware implementation
  • data sets
  • data processing
  • data analysis
  • data sources
  • real time
  • parallel architecture
  • hardware architecture
  • neural network
  • pipeline architecture