C
search
search
reviewers
reviewers
feeds
feeds
assignments
assignments
settings
logout
Celerity Hardware Implementation of the AES with Data Parallel and Pipelining Architecture inside the Round Function.
Shouwen Yang
Hui Li
Xiaotao Zhang
Gang Zhao
Published in:
TrustCom/ISPA/IUCC (2013)
Keyphrases
</>
hardware implementation
data sets
data processing
data analysis
data sources
real time
parallel architecture
hardware architecture
neural network
pipeline architecture