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Variable-Rate VLSI Architecture for 400-Gb/s Hard-Decision Product Decoder.
Vikram Jain
Christoffer Fougstedt
Per Larsson-Edefors
Published in:
IEEE Trans. Circuits Syst. I Regul. Pap. (2021)
Keyphrases
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vlsi architecture
low complexity
vlsi implementation
distributed video coding
rate allocation
low power
real time
motion estimation
high speed
low density parity check
bit plane
error concealment
mode decision
low cost
power consumption
ldpc codes