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Design of a 180 nm CMOS transceiver for implantable wireline communication, achieving 800 Mbps at BER<1e-12 with 22.4 dB of channel loss.
Naila Tasneem
Taufiq Ahmed
Ross M. Walker
Published in:
MWSCAS (2019)
Keyphrases
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cmos technology
physical layer
computer simulation
design process
multi channel
channel capacity
communication systems
communication channels