Low-Power and Area-Efficient Parallel Multiplier Design Using Two-Dimensional Bypassing.
Pankaj KumarRajender Kumar SharmaPublished in: J. Circuits Syst. Comput. (2017)
Keyphrases
- low power
- single chip
- power consumption
- high speed
- low power consumption
- vlsi architecture
- low cost
- logic circuits
- power dissipation
- gate array
- digital signal processing
- cmos technology
- high power
- power reduction
- nm technology
- general purpose
- wireless transmission
- image sensor
- parallel computing
- signal to noise ratio
- low complexity
- design process