A 1.8-V 22-mW 10-bit 30-MS/s Pipelined CMOS ADC for Low-Power Subsampling Applications.
Jian LiXiaoyang ZengLei XieJun ChenJianyun ZhangYawei GuoPublished in: IEEE J. Solid State Circuits (2008)
Keyphrases
- low power
- analog to digital converter
- power consumption
- mixed signal
- image sensor
- single chip
- vlsi circuits
- low cost
- low power consumption
- high speed
- wireless transmission
- digital signal processing
- high power
- cmos image sensor
- vlsi architecture
- data flow
- nm technology
- cmos technology
- power dissipation
- logic circuits
- power reduction
- solid state
- delay insensitive
- real time