Bipartitioning and encoding in low-power pipelined circuits.
Shanq-Jang RuanKun-Lin TsaiEdwin NaroskaFeipei LaiPublished in: ACM Trans. Design Autom. Electr. Syst. (2005)
Keyphrases
- low power
- high speed
- logic circuits
- cmos technology
- power dissipation
- vlsi circuits
- delay insensitive
- power consumption
- low cost
- power reduction
- mixed signal
- single chip
- vlsi architecture
- low power consumption
- high power
- digital signal processing
- image sensor
- real time
- signal processing
- wireless transmission
- gate array
- low voltage
- data flow
- signal processor
- ultra low power
- video data
- nm technology