The Design and Implementation of a Latency-Aware Packet Classification for OpenFlow Protocol based on FPGA.
Yu-Kai ChiuShanq-Jang RuanChung-An ShenChun-Chi HungPublished in: ICNCC (2018)
Keyphrases
- hardware architecture
- design process
- hardware design
- decision trees
- classification accuracy
- low cost
- hardware implementation
- fpga technology
- fpga implementation
- feature selection
- real time
- verilog hdl
- fpga hardware
- cross layer
- application layer
- field programmable gate array
- efficient implementation
- support vector machine