HSDPA Turbo Decoder ASIC in 0.13μm CMOS.
Christian BenkeserAndreas BurgTeo CupaiuoloQiuting HuangPublished in: ISSCC (2008)
Keyphrases
- circuit design
- turbo codes
- single chip
- packet loss
- distributed video coding
- error correction
- cmos image sensor
- low power
- low cost
- low complexity
- integrated circuit
- channel coding
- analog vlsi
- high speed
- power consumption
- error concealment
- decision feedback
- power supply
- hardware implementation
- design methodology
- decoding process
- application specific
- delay insensitive
- compressed images
- video codec
- hardware architecture
- successive approximation
- error control
- transform domain
- image sensor
- soft decision
- wireless channels