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FPGA design of FFT based intelligent accelerator with optimized Wallace tree multiplier for image super resolution and quality enhancement.

L. MalathiA. BharathiA. N. Jayanthi
Published in: Biomed. Signal Process. Control. (2024)
Keyphrases
  • image super resolution
  • nearest neighbor
  • hardware implementation
  • floating point
  • field programmable gate array
  • face recognition
  • pattern recognition
  • signal processing
  • low resolution