A Highly Efficient VLSI Architecture for H.264/AVC CAVLC Decoder.
Heng-Yao LinYing-Hong LuBin-Da LiuJar-Ferr YangPublished in: IEEE Trans. Multim. (2008)
Keyphrases
- highly efficient
- vlsi architecture
- low complexity
- mode decision
- distributed video coding
- variable length coding
- video coding standard
- motion estimation
- video coding
- bit rate
- computational complexity
- video codec
- coding efficiency
- error resilient
- motion compensation
- low density parity check
- wyner ziv
- video streaming
- coding method
- coding scheme
- rate distortion
- intra prediction
- motion compensated
- video compression
- digital video
- rate control
- search algorithm
- compressed video
- motion vectors
- error resilience
- power consumption
- bit plane
- bitstream
- macroblock
- low power