A Scalable and Low-Power FPGA-Aware Network-on-Chip Architecture.
Somnath MazumdarAlberto SciontiAntoni PorteroJan MartinovicOlivier TerzoPublished in: CISIS (2017)
Keyphrases
- low power
- network on chip
- power dissipation
- single chip
- cmos technology
- high speed
- low cost
- power consumption
- multi processor
- low power consumption
- vlsi architecture
- power reduction
- gate array
- software implementation
- routing algorithm
- digital signal processing
- logic circuits
- network simulator
- mixed signal
- data transfer
- shared memory
- hardware architecture
- hardware and software
- real time
- image sensor
- digital camera
- parallel algorithm
- design methodology
- hardware implementation
- multi channel