8.4 A 28Gb/s 1pJ/b shared-inductor optical receiver with 56% chip-area reduction in 28nm CMOS.
Tsung-Ching HuangTao-Wen ChungChan-Hong ChernMing-Chieh HuangChih-Chang LinFu-Lung HsuehPublished in: ISSCC (2014)
Keyphrases
- high speed
- cmos technology
- nm technology
- silicon on insulator
- metal oxide semiconductor
- focal plane
- image sensor
- analog vlsi
- low power
- power consumption
- cmos image sensor
- low cost
- circuit design
- single chip
- solid state
- low voltage
- power dissipation
- power reduction
- infrared
- integrated circuit
- chip design
- dynamic range
- parallel processing
- printed circuit boards
- mixed signal
- digital camera
- ibm power processor
- video camera
- vlsi implementation
- image processing algorithms
- imaging systems
- ultra low power