Hardware acceleration design of the SHA-3 for high throughput and low area on FPGA.
Argyrios SiderisTheodora SanidaMinas DasygenisPublished in: J. Cryptogr. Eng. (2024)
Keyphrases
- high throughput
- data acquisition
- hardware architecture
- low cost
- low power consumption
- hardware design
- microarray
- genome wide
- single chip
- low latency
- biological data
- hardware implementation
- real time
- fpga device
- systems biology
- protein protein interactions
- embedded systems
- automated image analysis
- dna sequencing
- hardware architectures
- xilinx virtex
- mass spectrometry
- field programmable gate array
- high speed
- data management
- genomic data
- hardware description language
- proteomic data