Low-Power Design Approach of 11FO4 256-Kbyte Embedded SRAM for the Synergistic Processor Element of a Cell Processor.
Toru AsanoJoel SilbermanSang H. DhongOsamu TakahashiMichael WhiteScott R. CottierTakaaki NakazatoAtsushi KawasumiHiroshi YoshiharaPublished in: IEEE Micro (2005)
Keyphrases
- low power
- single chip
- power consumption
- high speed
- gate array
- low cost
- low power consumption
- vlsi architecture
- logic circuits
- power reduction
- cmos technology
- cell processor
- digital signal processing
- power dissipation
- embedded systems
- ultra low power
- mixed signal
- highly parallel
- vlsi circuits
- nm technology
- vlsi implementation
- image sensor