A Multi-Standard Reconfigurable Viterbi Decoder using Embedded FPGA Blocks.

Lucia Bissi Pisana Placidi Giuseppe Baruffa Andrea Scorzoni

Published in: DSD (2006)

Keyphrases

hardware implementation
low cost
fpga implementation
field programmable gate array
embedded systems
noisy channel
signal processing
low complexity
hw sw
smart camera
image blocks
digital signal
reconfigurable hardware
decoding algorithm
viterbi algorithm
hidden markov models
low power
high speed
motion estimation