Hardware Implementation of (63, 51) BCH Encoder and Decoder For WBAN Using LFSR and BMA.
Priya MathewLismi AugustineSabarinath G.Tomson DevisPublished in: CoRR (2014)
Keyphrases
- hardware implementation
- shift register
- reed solomon
- error control
- distributed video coding
- decoding process
- noisy channel
- video codec
- fpga implementation
- low complexity
- error correction
- wyner ziv
- rate distortion
- efficient implementation
- turbo codes
- signal processing
- error resilience
- distributed source coding
- transform domain
- software implementation
- dedicated hardware
- video coding
- field programmable gate array
- video transmission
- bit rate
- successive approximation
- base layer
- machine learning
- rate allocation
- error concealment
- channel coding
- inter frame
- video compression
- packet loss
- bit errors
- video encoder
- image processing algorithms
- unequal error protection
- compressed video
- temporal correlation
- macroblock
- bit plane
- video quality
- random number generator
- low cost
- computer vision
- real time