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A novel low-power full-adder cell with new technique in designing logical gates based on static CMOS inverter.
Keivan Navi
Vahid Foroutan
Mostafa Rahimi Azghadi
Mehrdad Maeen
Maryam Ebrahimpour
M. Kaveh
Omid Kavehei
Published in:
Microelectron. J. (2009)
Keyphrases
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low power
logic circuits
power consumption
high speed
low cost
single chip
power dissipation
image sensor
cmos technology
high power
digital signal processing
vlsi architecture
low power consumption
wireless transmission
mixed signal
vlsi circuits
gate array
delay insensitive
nm technology