Reliable Low-Latency Viterbi Algorithm Architectures Benchmarked on ASIC and FPGA.
Mehran Mozaffari KermaniVineeta SinghReza AzarderakhshPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2017)
Keyphrases
- low latency
- viterbi algorithm
- high speed
- hardware implementation
- hardware architecture
- hidden markov models
- markov model
- dynamic programming
- single chip
- real time
- n gram
- high throughput
- highly efficient
- virtual machine
- field programmable gate array
- xilinx virtex
- integrated circuit
- data acquisition
- stream processing
- efficient implementation
- recurrent neural networks
- application specific
- data center
- cost effective
- markov chain
- distributed systems
- low cost
- state space
- reinforcement learning
- data mining