A Highly-Efficient Technique for Reducing Soft Errors in Static CMOS Circuits.
Srivathsan KrishnamohanNihar R. MahapatraPublished in: ICCD (2004)
Keyphrases
- highly efficient
- delay insensitive
- analog vlsi
- low cost
- high speed
- circuit design
- power reduction
- vlsi circuits
- cmos technology
- power consumption
- low power
- power dissipation
- multithreading
- chip design
- focal plane
- low complexity
- gray code
- power supply
- low voltage
- random access memory
- floating gate
- real time
- asynchronous circuits
- mixed signal
- sat solvers
- parallel processing
- search strategy