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A 2.5GHz, 6.9mW ΔΣ modulator with standard cell design in 45nm-LP CMOS using time-interleaving.
Paolo Madoglio
Ashoke Ravi
Luis Cuellar
Stefano Pellerano
Parmoon Seddighrad
Ismael Lomeli
Yorgos Palaskas
Published in:
ESSCIRC (2009)
Keyphrases
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power consumption
high speed
case study
real time
circuit design
linear programming
power supply
cmos technology
objective function
low cost
clock gating