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A discrete syntax for level-sensitive latched circuits having n clocks and m phases.
Glenn Jennings
Esther Jennings
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1996)
Keyphrases
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higher level
high speed
real time
neural network
machine learning
artificial intelligence
high level
reinforcement learning
artificial neural networks
finite number
lower level
levels of abstraction
discrete space
discrete version