Architecture and design of high-throughput, low-latency, and fault-tolerant routing algorithm for 3D-network-on-chip (3D-NoC).
Ben Akram AhmedAbderazek Ben AbdallahPublished in: J. Supercomput. (2013)
Keyphrases
- network on chip
- low latency
- high throughput
- fault tolerant
- routing algorithm
- packet switched
- interconnection networks
- fault tolerance
- power dissipation
- microarray
- multi processor
- network simulator
- real time
- wireless sensor networks
- multipath
- ad hoc networks
- high speed
- distributed systems
- data transfer
- highly efficient
- routing protocol
- shortest path
- load balancing
- data acquisition
- parallel algorithm
- power consumption
- mobile agent system
- cmos technology
- stream processing
- design methodology
- virtual machine
- network traffic
- multistage