Low-power design under variation using error prevention and error tolerance (invited paper).

Kwanyeob Chae Minki Cho Saibal Mukhopadhyay

Published in: LATW (2012)

Keyphrases

low power
error tolerance
invited paper
single chip
power consumption
low power consumption
vlsi architecture
low cost
logic circuits
high speed
power dissipation
digital signal processing
mixed signal
cmos technology
gate array
power reduction
association rules
embedded systems
model selection