Login / Signup
Clustered voltage scaling design technique for low-power hashing unit.
Andrey V. Korshunov
Pavel S. Volobuev
Alexander L. Stempkovsky
Sergey Gavrilov
Daria Ryzhova
Published in:
EWDTS (2017)
Keyphrases
</>
low power
low cost
single chip
power consumption
low power consumption
logic circuits
vlsi architecture
high speed
cmos technology
digital signal processing
design process
gate array
mixed signal
power reduction
low voltage
power dissipation
design methodology
low complexity
signal processor
real time