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Memory Efficient Hash-Based Longest Prefix Matching Architecture With Zero False +ve and Nearly Zero False -ve Rate for IP Processing.
Sanchita Saha Ray
Surajeet Ghosh
Bhaskar Sardar
Published in:
IEEE Trans. Computers (2022)
Keyphrases
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memory efficient
real time
parallel architecture
iterative deepening
processing elements
matching algorithm
network architecture
integral image
matching process
transitive closure
parallel processing
external memory
end to end
data distribution
pattern matching
bayesian classifiers
management system