A binary block matching architecture with reduced power consumption and silicon area requirement.
Marcelo M. MizukiUjjaval Y. DesaiIchiro MasakiAnantha P. ChandrakasanPublished in: ICASSP (1996)
Keyphrases
- power consumption
- block matching
- cmos technology
- low power
- power management
- motion estimation
- motion vectors
- energy efficiency
- motion compensation
- nm technology
- power saving
- optical flow
- video compression
- battery life
- high speed
- energy saving
- real time
- power dissipation
- block size
- low cost
- data flow
- motion field
- computer vision