Low-power frequency multiplier with one cycle lock-in time and 100ppm frequency resolution, for system power-management.
Rafael FriedZiv AzmanovPublished in: ISLPED (1996)
Keyphrases
- low power
- power consumption
- power management
- low cost
- high speed
- energy efficiency
- single chip
- vlsi circuits
- power reduction
- digital signal processing
- vlsi architecture
- high power
- low power consumption
- image processing
- energy saving
- data center
- power dissipation
- high resolution
- cmos technology
- database systems
- delay insensitive