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A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only).

Jianfeng ZhuDong WuYaru YanXiao YuHu HeLiyang Pan
Published in: FPGA (2011)
Keyphrases
  • low power
  • high speed
  • low cost
  • single chip
  • real time
  • computational complexity
  • signal to noise ratio
  • gaussian distribution