A 188fsrms-Jitter and -243d8-FoMjitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector.
Chanwoong HwangHangi ParkTaeho SeongJaehyouk ChoiPublished in: ISSCC (2022)