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Efficient pipelined tunable heterodyne notch filter implementation in FPGAs.
Asad Azam
Dhinesh Sasidaran
Karl E. Nelson
Gary E. Ford
Louis G. Johnson
Michael A. Soderstrand
Published in:
ISCAS (2000)
Keyphrases
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decision trees
hardware implementation
efficient implementation
cost effective
data flow
complexity analysis
neural network
design methodology
parallel architecture
hardware software
fpga technology