Design and Implementation of a Low Power Ternary Full Adder.
A. SrivastavaK. VenkatapathyPublished in: VLSI Design (1996)
Keyphrases
- low power
- logic circuits
- vlsi architecture
- power dissipation
- cmos technology
- single chip
- high speed
- power consumption
- low cost
- low power consumption
- ultra low power
- digital signal processing
- power reduction
- design process
- mixed signal
- design considerations
- wireless transmission
- signal processor
- gate array
- design methodology
- vlsi implementation
- efficient implementation
- general purpose
- real time