Power-Efficient Secured Hardware Design of AES Algorithm on High Performance FPGA.
Keshav KumarVijay SinghGaurav MishraB. Ravindra Babu.Nandita TripathiPramod KumarPublished in: IC3I (2022)
Keyphrases
- hardware design
- hardware implementation
- high efficiency
- detection algorithm
- learning algorithm
- single pass
- computational complexity
- k means
- neural network
- fpga implementation
- computationally efficient
- high speed
- multi agent systems
- optimal solution
- fine grained
- general purpose
- dynamic programming
- parallel architecture
- case study