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LTE Turbo Decoding Parallel Architecture with Single Interleaver Implemented on FPGA.
Cristian Anghel
Cristian Stanciu
Constantin Paleologu
Published in:
Circuits Syst. Signal Process. (2017)
Keyphrases
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parallel architecture
hardware implementation
systolic array
turbo codes
parallel processing
shared memory
parallel implementation
error correction
high level synthesis
synthetic aperture sonar
quality of service
parallel algorithm
pipelined architecture