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A PVT power immune compact 65 nm CMOS CSP design with a leakage current compensation feedback for CdZnTe/CdTe sensors dedicated to PET applications.

Pancha Yannick HertzJérôme Folla KamdemNoumbissi Sidze Laure VanessaWembe Tafo EvaristeEssimbi Zobo Bernard
Published in: Int. J. Circuit Theory Appl. (2022)
Keyphrases
  • power consumption
  • high speed
  • power dissipation
  • nm technology
  • circuit design
  • design process
  • sensor data
  • real time
  • np complete
  • low power
  • single chip
  • cmos technology
  • chip design
  • cmos image sensor