A new technique for estimating lower bounds on latency for high level synthesis.

Helvio P. Peixoto Margarida F. Jacome

Published in: ACM Great Lakes Symposium on VLSI (2000)

Keyphrases

high level synthesis
lower bound
upper bound
objective function
branch and bound
np hard
lower and upper bounds
parallel architecture
low latency
design space exploration
optimal solution
response time
online learning
computer aided
learning theory
prefetching
vc dimension
image processing