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Low Complexity and High Throughput VLSI Architecture for AVC/H.264 CAVLC Decoding.
Gwo Giun Lee
Chia-Cheng Lo
Yuan-Ching Chen
Sheau-Fang Lei
He-Yuan Lin
Ming-Jiun Wang
Published in:
ISCAS (2009)
Keyphrases
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high throughput
low complexity
vlsi architecture
mode decision
low density parity check
microarray
distributed video coding
computational complexity
decoding algorithm
motion estimation
turbo codes
data acquisition
bit rate
bit plane
video coding
video streaming
ldpc codes