Breaking the performance bottleneck of sparse matrix-vector multiplication on SIMD processors.
Kai ZhangShuming ChenYaohua WangJianghua WanPublished in: IEICE Electron. Express (2013)
Keyphrases
- sparse matrix
- parallel algorithm
- floating point
- parallel processing
- processor array
- mesh connected
- single instruction multiple data
- parallel architectures
- rows and columns
- massively parallel
- random projections
- arithmetic operations
- parallel implementation
- shared memory
- fixed point
- data analysis
- parallel computing
- random sampling
- data sets